1. Field of the Invention
The present invention relates to an access unit. More specifically, the present invention relates to an access unit for a static random access memory (SRAM).
2. Descriptions of the Related Art
Static random access memories (SRAMs) are often used in large quantities in system-on-chips (SOCs). To reduce the power consumption of mobile apparatuses using SOCs, the SOCs therein usually have only a single voltage as a power supply (VDD). If the supply voltage is excessively low when the data is written into an SRAM, the write operations often fail in the SRAM, which means that it is impossible to successfully alter the data stored in the SRAM access unit.
FIG. 1 is an oscillogram illustrating the variation of an output or an input signal of a conventional inverter. In this embodiment, curves 5 and 6 represent the variation of an output signal when the inverter is supplied with different supply voltages respectively, in which a supply voltage represented by the curve 5 is higher than that represented by the curve 6. Because the converter generally wavers between a high voltage level and a low voltage level, the midpoint of an output signal variation curve thereof is defined as an inverter trip point, for example, the curve 5 has a trip point 7 and the curve 6 has a trip point 8. In other words, the voltage below the trip point is considered as the low voltage level, while the voltage above the trip point is considered as the high voltage level. Because the supply voltage represented by the curve 5 is higher than that represented by the curve 6, the trip point 7 has a larger value than that of trip point 8.
FIG. 2(a) illustrates a schematic circuit diagram of a conventional SRAM access unit 1. The access unit 1 has a supply voltage VDD and a lowest voltage VSS respectively. The SRAM access unit 1 comprises two cross-coupled inverters 10, 11 configured to store data therein and two pass transistors 12, 13. The output terminal of the cross-coupled inverter 10 is connected with the input terminal of the cross-coupled inverter 11 to carry a voltage denoted as the node voltage DATA. On the other hand, the input terminal of the cross-coupled inverter 10 is connected with the output terminal of the cross-coupled inverter 11 to carry a voltage denoted as the node voltage DATAB. The pass transistors 12 and 13 are configured to electrically connect the cross-coupled inverters 10, 11 to bitlines BL and BLB respectively. The bitlines BL and BLB are opposite in phase to each other at all times, for example, when BL stays at a high logic level of “1”, BLB stays at a low logic level of “0”, and vice versa.
The cross-coupled inverters 10, 11 each comprise a pull-up PMOS transistor (i.e., PU1 and PU2) and a pull-down NMOS transistor (i.e., PD1 and PD2). The write operation of the SRAM access unit 1 is described as follows. To write the data to the SRAM access unit 1, one of the bitlines BL and BLB is pulled down to the low voltage level while the other remains at the previously charged voltage level, thus yielding a voltage difference between the bitlines BL and BLB. As a result, data is written into the SRAM access unit 1, i.e., data stored in the SRAM access unit 1 is successfully altered by the bitline that is pulled down to the low voltage level. Next, as shown in both FIGS. 2(a) and 2(b), when “0” is to be written into the SRAM access unit 1 with “1” stored therein, the word line WL turns on the pass transistor 12. At the same time, the voltage 101 of the bitline BL is pulled down, while the voltage (not shown) of the bitline BLB remains at a previously charged voltage. A drop in the voltage at the node DATA represents that the discharging current of the pass transistor 12 is larger than the charging current output from the inverter 10. Once the voltage at the node DATA drops below the input trip point of the inverter 11 (i.e., a mid-point value in the input voltage variation range), the node voltage DATAB begins to rise. The intersecting point 102 between the node voltages DATA and DATAB is defined as the flip point FP. Once the node voltage DATA passes through the SRAM flip point FP, the node voltage DATA becomes lower than the node voltage DATAB, in which case the write operation is successfully accomplished. A write margin WM represents the difference between the bitline signal voltage pulled down to a low value and the ground voltage upon the flip point FP occurring. In other words, a larger write margin means that it is easier to write data into the SRAM. For instance, in this example, when the supply voltage decreases, the flip point will be delayed, which means that the write margin WM will become smaller, making it harder to carry out the write operation.
In summary, conventional SRAM access units tend to experience failed write operations with low voltages. Accordingly, it is important to maintain the normal read and write operation of an SRAM access unit when there is a low voltage, thereby reducing the power consumption of the overall SRAM.